The present invention relates to a semiconductor device, in particular to a semiconductor device having a lateral element.
A general structure of a lateral high-voltage MOS (Metal Oxide Semiconductor) transistor (LDMOS transistor) formed over a p− epitaxial substrate is the structure of a RESURF (REduced SURface Field) type MOS transistor (refer to FIG. 1 in Non-patent Literature 1). In the structure, by optimizing an impurity concentration profile in an n-type drift region, a depletion layer expands even to a junction between the n-type drift region and a p− epitaxial region thereunder when a reverse bias is applied and a high breakdown voltage can be obtained.
When a transistor of a structure where a source electrode (or a p-type body region) and a p− epitaxial region are not electrically isolated from each other is used as a high-side element however, ground potential of the p− epitaxial region is destabilized by being pulled by a source voltage applied to the source electrode and a low-side element malfunctions. Consequently, a problem here is that such a transistor cannot be used as a high-side element and is limited to the application as a low-side element.
To cope with the problem, as structures usable even as a high-side element, there are two types of structures each of which has an n-type isolation region for electrically isolating a p− epitaxial region from a source electrode.
The first type has a configuration of forming an n-type isolation region stated above and then short-circuiting the n-type isolation region to a cathode region (refer to FIG. 1 in Patent Literature 1).
The second type has a configuration of forming an n-type isolation region stated above and then forming a p-type buried diffusion layer having a p-type impurity concentration higher than that of a p− diffusion region so as to be in contact with the n-type isolation region (refer to FIG. 1 in Patent Literature 2).